In digital communications, where signal synchronization devices are used, there are often requirements for DPLLs that can meet certain standards which define their filter response, and also have the capability of fast locking to a reference signal. Fast locking is especially desired upon power-up and during manual clock reference rearrangement. The normal locking time for a DPLL is inversely proportional to its filter response, so fast locking is very useful when standards prescribe a slow response (small corner frequency).
In prior art DPLL implementations (e.g. the embedded DPLL in Zarlink's MT90866 H.110 Compatible Digital Switch), some instances of fast-locking have been achieved by pushing the DPLL corner frequency to the higher frequency range in the fast-locking mode. Quick response of the DPLL output clock to frequency changes of the active input reference clock could be achieved, as well as close alignment of the output clock edge to the active input reference clock edge. Locking time was very small for fairly large DPLL corner frequencies (i.e. greater than 1 kHz).
However, previous implementations fail to meet two major fast-locking mode requirements. Firstly, the holdover frequency could be far from the guaranteed holdover stability if holdover mode was entered shortly after the fast-locking time passes. In the holdover mode, the DPLL produces a stable output at the last locked frequency. Other techniques had to be used to prevent DPLL from entering holdover mode until the expiry of the normal DPLL locking time, which is defined by its filter response. Secondly, the final output clock was not aligned to the active input reference after this short, fast-locking time. The phase difference from the active input reference clock to the output clock was proportional to the sampling error of the active input reference clock by the internal clock used in DPLL. This misalignment could cause failures in a system where that DPLL was used as clock synchronizer, especially in systems with high clock and data rate, comparable to the sampling error.